Performing a Gate-Level Functional Simulation with the Cadence Simulator Software
You can perform a gate-level functional simulation of a VHDL or Verilog HDL design that contains Intel-specific components with the Cadence Incisive Enterprise Simulator (IES) or Xcelium™ Parallel Simulator software:
Note: For more information about using
EDA simulators, refer to "Cadence Incisive Enterprise Simulator Support" in the
Intel® Quartus® Prime Pro Edition User Guide: Third-party
Simulation.
To continue with the simulation flow, perform a simulation with the Incisive Enterprise Simulator or Xcelium™ Parallel Simulator software.