Stratix® V Definition
The Stratix®V device family is optimized for high-performance and high-speed digital signal processing, bandwidth-centric applications and protocols, and data-intensive applications for 40G/100G. The Stratix® V family includes Stratix®GT, Stratix® V GX, Stratix®VGS, and Stratix®E devices, which contain transceiver circuitry and PCI Express hard IP blocks; except for the Stratix® E devices.
Stratix® V GT devices offer both 28 Gbps and 12.5 Gbps integrated transceivers, which are optimized for applications that require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communications systems and optical test systems.
Stratix® V GX devices have up to 66 integrated transceivers supporting backplane and optical modules with physical coding sublayer (PCS) and physical medium attachment (PMA) at serial data rates of up to up to 12.5 Gbps in C2 speed grade, up to 17 Gbps in C1 speed grade.
Stratix®VGS devices have 3,680 variable precision digital signal processing (DSP) blocks and up to 66 integrated transceivers supporting backplane and optical modules with physical coding sublayer (PCS) and physical medium attachment (PMA) at serial data rates of up to 12.5 Gbps.
Stratix® V E devices offer the highest logic density within the Stratix® V family with over one million logic elements (LEs) in the largest device.
Stratix®Vdevices provide dedicated circuitry that supports differential I/O standards at up to 1.6Gbps when using dynamic phase alignment (DPA). All Stratix® V devices also provide fractional PLLs (fPLL), and global, quadrant, and peripheral clock networks to increase performance, and provide precision clock synthesis, clock delay compensation, and zero delay buffering. Stratix®V family devices provide up to 32 fPLLs for each device.
Stratix®V family devices have dedicated circuitry to support physical layer functionality for serial protocols, such as PCI Express Gen1 and Gen2, Gigabit Ethernet, Serial RapidIO, XAU, GbE, GPON, and Interlaken. These protocols provide high-speed communication with application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), and other programmable logic devices (PLDs). You can use the PCI Express hard IP to implement the physical layer, data link layer, and transaction layer of the PCI Express protocol stack. The PCI Express hard IP uses embedded dedicated logic to implement the PCI Express protocol stack.
The Stratix®V family device architecture supports the M20K and the MLAB blocks. M20K memory blocks implement single-port, dual-port, and true dual-port memory. MLABs implement single-port and dual-port memory. Stratix®V family devices offer support for remote configuration updates. Stratix®V family devices also contain embedded DSP blocks that enable efficient implementation of high-performance filters and multipliers. The Adaptive Logic Module (ALM) of the Stratix®V family device architecture provides advanced features with efficient logic utilization.
The memory blocks of Stratix®V family devices can implement shift registers and various types of memory with or without parity bits, including single-port, simple dual-port, or true dual-port RAM; ROM; FIFO buffers; and shift registers. These blocks can also emulate SERDES functions for low-speed LVDS channels. In addition, Stratix®V family device I/Os have dedicated circuitry to assist with the implementation of high-speed interfaces to external memory devices such as double data rate 2 (DDR), DDR3, quad data rate (QDR) II, RLDRAM II, and RLDRAM III.