Synthesis

Allows you to choose options for the HDL files.

Create HDL design files for synthesis—

HDL languge for the output files. You can select Verilog or VHDL design files

Note: The Platform Designer interconnect is written in Verilog.

Create timing and resource estimates for third-party EDA synthesis tools

If turned on, Platform Designer generates non-functional Verilog Design File (.v) that a third-party EDA synthesis tool can read. This file estimates timing and resource usage for the IP component. The generated netlist file name is <your_ip_component>_name.v.

Create Block Symbol File (.bsf)

If turned on, Platform Designer creates a (.bsf) file to use in schematic Block Diagram File (.bdf) designs.

IP-XACT

If turned on, Platform Designer creates an IP-XACT representation of the generated system.

Generate IP Core Documentation

If turned on, Platform Designer generates the documentation for the IP core.