To perform a gate-level functional simulation of a Verilog HDL design with command-line commands

  1. If you have not already done so, set up the Incisive Enterprise Simulator Working Environment.
  2. To create a work library in the project directory, type the following command at the command prompt:
    mkdir <work library>
    Note:

    Intel recommends using the IES (Verilog or VHDL) default library names when you create a library. You should name the IES software libraries as follows:

    • When you run the IES software independently from the Intel® Quartus® Prime software, you should name your library work.
    • When you run the IES software automatically from the Intel® Quartus® Prime software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
  3. Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.
  4. Edit the cds.lib and hdl.var files as follows:
    File Name File Contents Function
    cds.lib DEFINE<work library> ./work Maps the <work library> to the physical location of the work library.
    hdl.var DEFINE WORK<work library> Maps the IES variable WORK to the <work library>.
  5. To compile the appropriate project files into the work library, type the following commands at the command prompt from within the project directory:
    ncvlog<testbench file>.v
    ncvlog<design name>.v
  6. To elaborate and simulate the design, type the following command at the command prompt:
    ncelab <work library>.<top-level entity name>  
    ncsim <work library>.<top-level entity name>