Commands for EDA Tools

Processing Menu Commands

You can use the Start Test Bench Template Writer command to generate Verilog Test Bench File (.vt) Definition and VHDL Test Bench File (.vht) Definition for simulation with other EDA simulation tools.

You can use the Start EDA Netlist Writer to generate VHDL Output File (.vho) Definition, SystemVerilog Output File (.svo) and for a design. You can compile a design and then specify different EDA tool settings and regenerate the netlist files without recompiling the design.