PLL Compensation Mode logic option

This logic option specifies the routing path of the PLL feedback clock and adjusts the delay chains in the PLL.

You can specify the following settings for this logic option:

• Direct—Minimizes the jitter at the PLL output. You can produce the smallest possible jitter by minimizing the length of the feedback path with no compensation.
• External Feedback—Positions the clock edge at the clock output pin to occur before the clock edge at the clock input (reference) pin. You can position the clock edge by the varying the board trace delay placed between the clock output pin and the external feedback input pin. Ideally, this mode compensates for any difference in the delay between the following two paths:
  • Clock input pin to the PLL phase frequency detector (PFD) input
  • External feedback input pin to the PLL PFD input
• LVDS—Maintains the same data and clock timing relationship seen at the pins of the internal SERDES capture register. Ideally, this mode compensates for the delay of the LVDS clock network, plus any difference in delay between the following two paths:
• • Data pin to the SERDES capture register
  • Clock input pin to the SERDES capture register

The compensation mimic path is designed to mimic the clock and data delay of the receiver side.

• Normal—Positions the clock edge at an I/O element (IOE) or logic element (LE) register to occur at the same time as at the clock input pin. Ideally, this mode compensates for the clock network and for the delay from the clock input pin to the PLL PFD input. Because you cannot compensate for the delay in the first stage of the input buffer, you must use the delay chain for compensation.
• Source Synchronous—Maintains the same data and clock timing relationship seen at the pins at any IOE register. Ideally, this mode compensates for the delay of the clock network used, plus any difference in delay between the following two paths:
• • Data pin to the IOE register input
  • Clock input pin to the PLL PFD input

There is a delay cell block in the feedback path that compensates for the timing differences between the SE and Diff input delay in the I/O register and wire delay.

• Zero Delay Buffer—Creates a zero delay between a clock edge at the clock input pin and the clock output pin. This setting consumes a clock output pin to provide the output buffer delay compensation. Ideally, this mode compensates for the delay from the clock input pin to the PLL PFD input, plus the delay from the PLL output to the clock output pin. If the input clock and feedback buffers use different I/O standards, you must compensate for the delay difference with a delay chain.

This option is available for the Stratix^® V device family only.