Input Delay from Pin to Internal Cells logic option

A logic option that specifies the propagation delay from an input or bidirectional pin to logic and embedded cells within the device. Use this advanced option after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.

This option is useful for fine-tuning the I/O timing of your design and meeting tSU and tH requirements.

This option must be assigned to an input or bidirectional pin or it is ignored. This option is available for supported device (Arria^® II GX, Cyclone^® III, Cyclone^® IV, MAX^® II, and MAX^® V) families.