Output Buffer Delay logic option

A logic option that specifies the delay value in picoseconds (ps) for the programmable output buffer delay. Enabling this option improves the output duty cycle; however, delay across the output buffer may increase. For information about output buffer delay control, refer to the Output Buffer Delay Control logic option.

This option is available for supported device (Arria^® II GZ, Stratix^® III, Stratix^® IV, and Stratix^® V) families.