DQS Bus to Input Register Delay logic option

A logic option that increases the propagation delay of the DQS clock signal to input register of the target pin. This is an advanced option that should be used only after compiling a design, checking the I/O timing, and verifying that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the specific device family.

This option must be assigned to a DQ or DQS pin, otherwise it is ignored.