Input Ports

data[]

Yes

Data input to the memory.

Input port LPM_WIDTH wide.

address[]

Yes

Address input to the memory.

Input port LPM_WIDTHAD wide.

we

Yes

Write enable input. Enables write operations to the memory when high.

Required if inclock is not present. If only the we port is used, the data on the address[] port should not change while we is high. If the data on the address[] port changes while the we port is high, all memory locations that are addressed are overwritten with data[].

inclock

No

Synchronizes memory loading.

If the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock signal. If the inclock port is not used, the we port acts as an enable for asynchronous write operations. In addition, if the inclock port is not used, the LPM_INDATA and LPM_ADDRESS_CONTROL parameters should be set to "UNREGISTERED".

outclock

No

Synchronizes q outputs from memory.

The addressed memory content-to-q[] response is synchronous when the outclock port is connected, and asynchronous when it is not connected. In addition, if the outclock port is not used, the LPM_OUTDATA parameter should be set to "UNREGISTERED".