Performing a Gate-Level Simulation with the Riviera-PRO Software

You can use the Aldec Riviera-PRO software to perform a gate-level (post-fit) simulation of a VHDL or Verilog HDL design that contains Intel-specific components.

The Riviera-PRO software not only has its own native command-line commands, but also supports ModelSim® command-line commands. The ModelSim® commands are the commands that start with "v", such as vlib.

  1. If you have not already done so, set up the Riviera-PRO working environment.
  2. Perform a full compilation.
  3. To generate gate-level (post-fit) simulation files from the command line, run the Intel® Quartus® Prime EDA Netlist Writer by typing:
    Option Description
    Verilog
    quartus_eda --simulation --tool=rivierapro --format=verilog <design> <project directory>
    VHDL
    quartus_eda --simulation --tool=rivierapro --format=vhdl <design> <project directory>
    Note: If you already selected the Riviera-PRO software as your simulation tool in a Intel® Quartus® Prime project, use the command
    quartus_eda <design>
    .
  4. Start the Riviera-PRO simulator in command-line mode:
    Option Description
    Linux
    /<Riviera_PRO root directory>
    Windows
    runvsimsa
  5. Create a working library:
    alib/vlib <library name>
  6. Specify theworklib variable:
    set worklib <library name>
    <library name> is typically specified as work.
  7. Map the logical name onto library index:
    amap/vmap <library name>
  8. Compile the Verilog HDL or VHDL simulation library files:
    1. Create a library for the simulation library files, type the following command:
      alib/vlib <simulation library name> 
    2. Choose the Intel post-fit libraries provided with the Intel® Quartus® Prime software for your design.
    3. Compile the files chosen in the previous step:
      alog/vlog/acom/vcom -dbg -work <simulation library name> <file name>
      If you do not need to debug your design, you should compile the source files without the -dgb switch, which can decrease simulation speed.
  9. Compile the Verilog HDL or VHDL design and test bench files:
    alog/vlog/acom/vcom -dbg -work <library name> <file name>
    If you do not need to debug your design, compile the source files without the
    -dgb
    switch, which can decrease simulation speed.
  10. Initialize the simulation:
    Option Description
    Verilog
    asim/vsim -t 1ps -L <library1> -L <library2> ... <top module> 
    VHDL
    asim/vsim -t 1ps -sdftyp /UUT=<sdo file> -L <library1> -L <library2> ... <top module>
    Switch/Argument Description
    -t Specifies the time scale to be simulated in ps
    -L Allows you to specify multiple simulation libraries that you have already compiled.
    Once you initialize the simulation, the simulation database (.asdb file) is created.
  11. Run the simulation:
    run<running time>

To run the simulation until the end, leave out the <running time> argument.

Use the command transcript file <file_name> to record messages.

Note: For more information about using EDA simulators, refer to the Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation.