Guidelines for Mapping Unequal Number of Inputs and Outputs

When mapping unequal numbers of inputs and outputs, use the following guidelines:

Use a text editor to modify the appropriate Library Mapping File (.lmf) Definition if a Intel® Quartus® Prime function has more or fewer ports than an equivalent third-party function. Include place holders that equate the number of EDIF function ports with the number of Intel® Quartus® Prime logic function ports for a particular piece of logic. You can use spaces, closed quotes, or global VCC or GND designations as placeholders.
Note: If an EDIF cell generated from a third-party design tool function contains more inputs than a Intel® Quartus® Prime logic function, the Intel® Quartus® Prime software ignores the extra ports and issues a warning message. Also a warning message appears if an EDIF cell contains more outputs than the equivalent Intel® Quartus® Prime function, and the extra EDIF output signal feeds another function.

Example of More Input Pins than EDIF Input Ports:

If there are more Intel® Quartus® Prime input pins than EDIF input ports, map the extra Intel® Quartus® Prime input pins to VCC or GND to make them inactive. Be careful to choose appropriate default values.

In this example, the active-low PRN pin of the Intel® Quartus® Prime DFF primitive must be driven by VCC to become inactive. The placeholder is the global high or global low signal defined by the EDA tool.

BEGIN 
FUNCTION dff (CLRN, CLK, D, PRN) 
RETURNS (Q) 
FUNCTION "LS174" ("-CL", "CLOCK", "D<0>", "VCC") 
RETURN ("Q<0>") 
END

Example of Fewer Input Pins than EDIF Input Ports:

If there are fewer Intel® Quartus® Prime input pins than EDIF input ports, insert an extra comma (,) at the end of the Intel® Quartus® Prime function input list for each of the EDIF input ports that cannot be mapped to the Intel® Quartus® Prime function.

In this example, only the A<0> and B<0> ports of the LS21 function are mapped onto the AND2 primitive. The C<0> and D<0> ports must not be driven by signals within the . A signal that drives an unmapped pin is reported as a node without a destination.

BEGIN 
FUNCTION and2 (IN1, IN2, , ) 
RETURNS (OUT) 
FUNCTION "LS21" ("A<0>", "B<0>", "C<0>", "D<0>") 
RETURNS (" Y<0>") 
END

Example of More Output Pins than EDIF Output Ports:

If there are more Intel® Quartus® Prime output pins than EDIF output ports, the RETURNS section for the EDIF function must contain an extra comma (,) and double quotation marks (") for each of the unmapped outputs in the Intel® Quartus® Prime function.

In this example, the Intel® Quartus® Prime software automatically removes the Q1 and Q2 outputs of the custom bill function and all logic within the bill function required to generate these outputs.

BEGIN 
FUNCTION bill (CLRN, BOG, V, PRTY) 
RETURNS (Q0, Q1, Q2) 
FUNCTION "TED" ("-CL", "-BGS", "Z", "-PRTY") 
RETURNS ("Q0", "", "") 
END

Example of Fewer Output Pins than EDIF Output Ports:

If there are fewer Intel® Quartus® Prime output pins than EDIF output ports, the RETURNS section for the Intel® Quartus® Prime function must contain commas for each of the EDIF ports that do not map to a Intel® Quartus® Prime function port.

In this example, if the -Q<0> port drives a net (or signal) within the EDIF netlist, the Intel® Quartus® Prime software generates the warning Net has no source, because no source pin is driving the signal.

BEGIN 
FUNCTION dff (CLRN, CLK, D, PRN) 
RETURNS ( ,Q) 
FUNCTION "LS74" ("-CL", "CLOCK", "D" <0> , "-PR") 
RETURNS ("-Q <0> ", "Q <0> ") 
END