TMC-20203: Setup-Failing Paths with High Fabric Interconnect Delay


Violations of this rule identify paths with a "fabric-IC-only slack" below the maximum setup slack threshold parameter.

Timing paths may fail setup without any delay contributions from cell delay, local interconnect delay, or clock skew. If those components are removed from the overall slack, what remains is the path's fabric interconnect delay, as well as the combination of the combination of clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These requirements together constitute a path's fabric-IC-only slack. A negative fabric-IC-only slack implies that you must reduce the fabric interconnect on a path or its requirements.

For example, consider a path with a combined μtCO, μtSU, and fabric interconnect delay that together exceeds its target clock period. Such a path is likely to fail setup, and as such its fabric-IC-only slack is negative. Reduce the fabric interconnect on a path or relax its setup requirements.


maximum_setup_slack—a violation is reported for timing paths that have a setup slack below the value of this parameter.


Restructure the path to increase its fabric-IC-only slack:

  • Decrease the hold requirement on one or more of its connections. A connection may be shared across multiple timing paths.
  • Adjust placement constraints to reduce the physical distance between each node on the path.
  • Reduce congestion in the nearby area.
  • Adjust SDC constraints to relax the path's setup constraint.
  • If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered.
  • If the launch and latch clocks are different, ensure their relationship is properly constrained.





Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10