TMC-20202: Setup-Failing Paths with High Logic Delay


Violations of this rule identify paths with a "logic-only slack" below the maximum setup slack threshold parameter

Timing paths may fail setup without any delay contributions from fabric interconnect delay or clock skew. If those components are removed from the overall slack, what remains is the path's logic delay (cell delay + local interconnect delay), as well as the combination of the clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These components together constitute a path's logic-only slack. A negative logic-only slack implies that the path's logic levels must be reduced or its requirements must be relaxed to meet timing.

For example, consider a path with a combined μtCO, μtSU, cell delay, and local interconnect delay that together exceeds its target clock period. Such a path is likely to fail setup, and as such its "logic-only-only slack" is negative. Reduce logic levels on the path or relax its setup requirements to close timing.


maximum_setup_slack—a violation is reported for timing paths that have a setup slack below the value of this parameter.


Restructure the path to increase its intrinsic margin or reduce the logic delay on the path:

  • Add pipeline registers.
  • Refactor logic on the path to reduce logic levels.
  • Ensure register retiming optimization is unblocked on the path.
  • Adjust SDC constraints to relax the path's setup constraint.
  • If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered.
  • If the launch and latch clocks are different, ensure their relationship is properly constrained.





Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10