TMC-20201: Setup-Failing Paths with High Clock Skew


Violations of this rule identify paths with a "clock-skew-only slack" below the maximum setup slack threshold parameter.

Timing paths may fail setup without any delay contributions from cell delay or interconnect delay. If those components are removed from the overall slack, what remains is the path's clock skew, as well as the combination of its clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These components together constitute a path's "clock-skew-only slack." A negative "clock-skew-only slack" implies that the clock skew between the path's endpoints must be reduced or its requirements must be relaxed to meet timing.

For example, consider a path with a combined μtCO, μtSU, and clock skew that exceeds its target clock period. Such a path is likely to fail setup, and as such its "clock-skew-only slack" is negative. Reduce clock skew between the path's endpoints or relax its setup requirements to close timing.


maximum_setup_slack—a violation is reported for timing paths that have a setup slack below the value of this parameter.


Restructure or re-constrain the path to increase its intrinsic margin or reduce its clock skew using any of the following:

  • Ensure the launch and latch clocks are routed globally.
  • Resize clock regions.
  • Redesign cross-clock transfers.
  • Adjust SDC constraints to relax the path's setup constraint.
  • If the launch and latch clocks are different, ensure their relationship is properly constrained.
  • If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered (See the "RAM Summary" and "DSP Register Packing Details" Fitter report tables for more information).





Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10