TMC-20200: Setup-Failing Paths with Impossible Requirements


Violations of this rule identify paths with an "intrinsic margin" below the value of the maximum setup slack parameter.

Timing paths may fail setup without any contributions from cell delay, interconnect delay, or clock skew. If those components are removed from the overall slack, what remains is the combination of clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These requirements together constitute a path's intrinsic margin. A negative intrinsic margin is considered an impossible requirement to meet.

For example, consider a path with a combined μtCO and μtSU that exceeds its target clock period. Such a path has a negative intrinsic margin and has an impossible setup requirement. Relax the setup relationship to close timing.


maximum_setup_slack—a violation is reported for timing paths that have a setup slack below the value of this parameter. Default value is 0.000.


Restructure or re-constrain the path to increase the intrinsic margin using one of the following:

  • Adjust SDC constraints to relax the path's setup constraint.
  • If the launch and latch clocks are different, ensure their relationship is properly constrained.
  • If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered.





Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10