SGR-30020: Synchronous and Asynchronous Ports of the Same Register Driven by the Same Signal Source


A signal race problem can occur if synchronous and asynchronous ports of the same register are driven by the same signal source.

Figure 1. Signal Race Problem Example. The following image shows an example of the same signal source driving the synchronous port and the preset port of the same register:

The Design Assistant does not report a violation if the signal source is from a negative-edge sensitive register of the same clock, and if the source register is directly feeding the D and the clrn port.

Figure 2. Signal Race Problem Example


The same signal source should not drive the synchronous port and any other asynchronous port of the same register, for example aload, adata, preset, and clear (active high and active low).




Analysis and Elaboration

Device Family

  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX