RES-50003: Asynchronous Reset Missing Timing Constraint


The release of asynchronous reset signals must not only be followed by a reset synchronizer chain, but must also be constrained in a way that prevents the Timing Analyzer from analyzing asynchronous reset signals as timed, synchronous transfers. Static timing analysis cannot accurately analyze such paths.

Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:

  • The reset signal is from an unconstrained input
  • The clock domain of the reset signal is unrelated/asynchronous to the latching domain of the register being reset


When a reset transfer is intended to be asynchronous, either constrain it with a set_false_path or set_clock_groups -asynchronous constraint, or relax the timing on the transfer by constraining it with a set_max_delay constraint whose value is greater than the latch clock's period.

Figure 1. Reset Synchronizer Chain Example. The following example shows a reset synchronizer chain. To prevent Design Assistant violation RES-50003, specify a false path, asynchronous clock group, or relaxing maximum delay on the transfers from the async reset source to all of the registers’ async reset pins.




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Device Family

  • Intel® Agilex™
  • Intel® Stratix® 10
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10