RES-50002: Asynchronous Reset is Insufficiently Synchronized


When synchronizing an asynchronous reset signal with a reset synchronizer chain, the chain must contain at least two registers. Otherwise, the chain may not be robust enough at synchronizing the reset signal to prevent metastability.

Figure 1. Single-Stage Reset Synchronizer Chain Example. The following example shows an example of a reset synchronizer chain with only one stage, which triggers the RES-50002 Design Assistant violation. To prevent a violation, the register must be followed by at least one other register also latched by clka and reset by the same asynchronous reset signal.


Ensure that all reset synchronizer chains contain at least two registers. Refer to ../rlc1584464111560.htm#rlc1584464111560 for instructions on how to form such a chain.




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Device Family

  • Intel® Agilex™
  • Intel® Stratix® 10
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10