RES-50001: Asynchronous Reset Is Not Synchronized


When using an asynchronous reset, the release of the reset signal must be synchronous with the register being reset. Otherwise, the register may experience metastability upon reset release.

Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:

  • The reset signal is from an unconstrained input
  • The clock domain of the reset signal is unrelated/asynchronous to the latching domain of the register being reset
Figure 1. Unsynchronized Reset Example. The following example shows an unsynchronized reset that triggers Design Assistant violation RES-50001. To prevent the violation, the asynchronous reset must feed a reset synchronizer chain, the output of which can reset the register.


Synchronize the release of asynchronous reset signals with a reset synchronizer chain. Ensure that the reset signal feeds the asynchronous reset pins of a sequence of two or more registers, with no fan-out in between them, and with the head of the chain fed by a constant. You can use the output of the last register as a reset signal that is synchronous with the clock domain of the chain.




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Device Family

  • Intel® Agilex™
  • Intel® Stratix® 10
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10