PDI-20100: Platform Designer Interconnect Timing Violation


The design contains failing timing path between Platform Designer interconnect components.


Add pipeline stages between <componentA> and <componentB> by following these steps in Platform Designer:

  1. Open the Platform Designer system that has this violation.
  2. In the right-hand pane, go to Domains tab and click on Show System with Interconnect button, which launches the System with Platform Designer Interconnect window.
  3. In the System with Platform Designer Interconnect window, go to Memory-Mapped Interconnect tab.
  4. In the Interconnect drop-down menu, select the interconnect that has the failing path (for example, mm_interconnect_N in the following image).
  5. Select the Show Pipelinable Locations check box. This results in displaying all pipelinable locations.
  6. Identify components A and B in the interconnect, right-click on their gray boxes and select Pipelined.





Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™