Fitter Feature Specific Reports

The clock delay controls provide a delayed signal on the global clock network from the dual-purpose clock pins. This report appears only if the design includes clock delay controls.

• Name shows the name of the clock delay control.
• Source I/O shows the I/O pin in the design that feeds the clock delay control.
• Location shows the location of the clock delay control.
• Delay Chain Mode shows the delay chain mode. If the value is static, the delay chain settings are shown. If the value is none, no delay chain is added to the clock delay control.
• Delay Chain Setting shows the delay chain setting from 0 to 63 on the clock delay control's delay chain. The smallest delay setting is 0 and the largest delay setting is 63.

Reports register control signal path signal names, locations, fan-outs, and types for all clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, clear, read enable, write enable, and output enable signals used in the design.

• Name shows the name of the register control signal path signal.
• Pin # shows the pin number.
• Migration Pin# shows the pin number of the largest compatible migration device.
• Location shows the location of the control signal.
• Fan-Out shows the fan-out for the pin.
• Usage shows the signal usage.
• Global Usage shows the global usage of the signal.
• Global shows whether the signal is a global signal.
• Global Resource Used shows the type of global resource used for the control signal.
• Global Line Name shows the name of the global line used for the signal.

Summarizes information about the delay chain Definition in your design. This report lists the node name and pin type. Delay chains are listed in terms of their delay chain fan-out setting and actual delay in ps.

Reports information regarding SERDES Definition receiver usagein device families with transceivers. The parameter values may include Name (the <SERDES receiver instance>), signal source names from Clock0, Enable0, Enable1, and Data Width. This report appears only if the design includes SERDES receivers.

Reports information regarding SERDES Definition receiver with dynamic phase alignment (DPA) Definition usage in device families with transceivers, including parameter values specified when instantiating the LVDS_RX. The parameter values may include Name (the <SERDES receiver instance>), signal source names from Clock0, Core Clock, Enable0, Data Realigner, Reset, DPLL Reset, Data Width, and FIFO (Enabled | Disabled). This report appears only if the design includes SERDES receivers.

Reports information regarding SERDES Definition transmitter usage in device families with transceivers, including parameter values you specified either by using the parameter editor, or by editing a text file. The parameter values may include Name (the <SERDES transmitter instance>), signal source names from Clock0, Enable0, and Data Width. This report appears only if the design includes SERDES transmitters.

Summarizes information about the parameter settings for each delay-locked loop (DLL) Definition. One row is included for each DLL atom. The report includes the following information:

• DLL shows the instance name of the DLL atom.
• Location shows the location occupied by the DLL.
• Input Frequency shows the input frequency of the DLL.
• Fast Lock / Low Jitter shows whether the DLL is configured for fast lock or low jitter operation.
• Cycles Needed to Lock shows the number of cycle needed to lock the DLL.
• delayctrlout Mode shows the modes of delay control out. This column only appears if your design targets an FPGA device.
• Delay Buffers in Loop shows the number of delay buffers in the loop . This column only appears if your design targets an FPGA device.
• Delay Buffer Mode shows whether the delay buffer mode is in high frequency or low frequency mode. This column only appears if your design targets an FPGA device.
• offsetctlrout Mode shows the setting of the offset control out mode. This column only appears if your design targets an FPGA device.
• Static Offset shows the setting of the static offset. This statistic is only shown if the offset control out mode is set to static, using the altdqs Intel^® FPGA IP. This column only appears if your design targets an FPGA device for compilation.

Summarizes information about the parameter settings for each DQS I/O Definition I/O pin or nDQS I/O pin in your design. This report appears only if your design targets a supported device (Arria^® II Series, Stratix^® IV, and Stratix^® V ) family for compilation.

• DQS shows the instance name of the DQS pin.
• Associated nDQS shows the instance name of the associated nDQS pin (if any). This column appears only if you specify an FPGA device.
• Location shows the location of the I/O pin assigned by the Fitter.
• X Location shows the X coordinate location of the I/O pin assigned by the Fitter.
• Y Location shows the Y coordinate location of the I/O pin assigned by the Fitter.
• DQS Bus Width shows the DQS bus width.
• Input Frequency shows the input frequency in MHz.
• Associated DLL shows the instance name of the associated DLL controller (if any).
• DLL-Controlled Phase Shift shows the amount of phase shift, in degrees, implemented by the associated DLL controller.
• Delay Buffers shows the number of delay buffers. This column appears only if your design targets an FPGA device.
• Delay Buffer Mode shows the delay buffer mode. This column appears only if your design targets an FPGA device.
• Offset Control shows whether the phase shift offset control is turned on or off. This column appears only if your design targets an FPGA device.
• Control Latches shows whether the control latches are turned on or off. This column appears only if your design targets an FPGA device.
• Edge Detect shows whether the edge detection circuitry is turned on or off. This column appears only if your design targets an FPGA device.
• Gated DQS shows whether the DQS I/O pin is gated or not. This column appears only if your design targets an FPGA device.

Reports information regarding usage of DSP block Definition. This section is omitted if the design does not include DSP blocks. The report includes the following information:

·Name shows the name of the node contained in a DSP block.

·Mode shows the mode in which the DSP block is operating

·Location shows the location on the DSP block where the instance is located.

·Sign Representation shows the sign representation of the DSP block.

·Register(s) lists all the registers available for the DSP block and whether or not they were used. Types of registers can include:

oData Input registers

oPipeline registers

oOutput registers

·Input Cascadedindicatesthe use of input shift register chains in the DSP block.

·Has Output Adder Chain shows the use of output adder chains in the DSP block.

This section is omitted if the design does not include DSP blocks. The report lists the following information:

• Statistic shows the operating modes of the DSP blocks.
• Number Used shows the number of each type of DSP block used in the device.

Summarizes information about the modes usable by DSP block Definition. These modes can include:

• Independent 9x9
• Independent 18x18 packed
• Independent 18x18
• Independent 18x18 with 32-bit result
• Independent 18x18 plus 36
• Sum of two 18x18 with systolic register
• Sum of four 18x18
• Sum of two 18x18
• Complex 25x18
• Independent 27x27
• Sum of two 27x27
• Sum of two 36x18
• Integer 36x36 / Complex 18x18
• Independent 36x18
• Independent 54x54
• Independent 72x18
• Floating Point Multiplier
• Floating Point Adder
• Floating Point Sum of Products
• Floating Point Accumulation of Products
• Floating Point Vector Mode 1
• Floating Point Vector Mode 2

These reports provide information regarding usage of DSP block Definition in Intel^® Arria^® 10 and Intel^® Stratix^® 10 designs. This section is omitted if the design does not include DSP blocks. The summary report lists how many DSP blocks are fully registered, partially registered, or unregistered. It also lists how many DSP blocks the software cannot register pack.

The software generates these reports during register packing in the Plan phase. When the Plan stage completes successfully, the report shows the DSP register packing results. Additionally, the software generates the reports before DSP block merging; therefore, they include DSP instances that may later disappear because they are combined with another block during DSP merging. Reporting DSP block register packing early allows you to fix problems that prevent DSP block register packing with quicker iterations because you do not have to perform a full compile to see the results.

For each DSP block, the Reasons Preventing Register Packing column describes why the software could not pack external register candidates into that particular DSP block. If no reasons are given, the software could not find a candidate register. The Fixed Point DSP Register Packing Summary lists the number of DSP blocks affected by each reason:

• Overuse: Control signal overuse (requires more clock/enable or clears than are available)
• Mismatch: Control signal mismatch (different clock/enable or clears pack to same register bank)
• Restricted: Subject to a compiler or user restriction
• Inverted: Programmable invert not available in DSP block
• Vcc: Input tied to Vcc
• NoOuptutFF: Output connected to something other than a register
• MultFanout: Output has multiple fan-outs
• MixedClears: Conflicting use of synchronous and asynchronous clears on adjacent registers (Intel^® Stratix^® 10 devices only)

Reports information about the embedded cells in the device. The report lists the following information:

• Cell # shows the embedded cell number.
• Name shows the name of the design entity located in the embedded cell.
• Mode shows whether the embedded cell is in product term or RAM mode.
• Turbo shows whether the TurboBit logic option is turned on or off.

Summarizes information about the RAM memory blocks in the design, including name, mode, location, port width, port depth, size, the number of RAM memory blocks used to implement the memory, and the Memory Initialization File (.mif) Definition, if a Memory Initialization File was specified for the initial contents of the memory.

The Fitter Resource Usage Summary report and the Fitter RAM Summary report both report information about RAM memory blocks, but the values reported may differ. The Fitter Resource Usage Summary report shows the number of packed RAM memory blocks, which equals the number of blocks actually used. The Fitter RAM Summary report shows a count of each user-instantiated logical memory blocks and the number of spread out RAM memory blocks. Because a physical memory block can be used by more than one logical memory block through packing, the Fitter RAM Summary report shows a Location column, indicating where multiple logical memories are used. The report lists the following information:

• Name shows the name of the memory block.
• Type shows the type of memory block you specified.
• Mode shows the mode of the memory block.
• Port A Depth, Port A Width shows the width and depth, in bits, of data on port A.
• Port B Depth, Port B Width shows the width and depth, in bits, of data on port B.
• Size shows the size of the memory block, which is equal to depth multiplied by width.
• Physical Bits Used shows the physical RAM bits used.
• M512s shows the number of M512 memory blocks used to implement the memory.
• M4ks shows the number of M4K memory blocks used to implement the memory.
• M-RAMs shows the number of M-RAM used to implement the memory.
• MIFshows the MIF specified for the initial contents of the memory.
• Location shows the location (x and y coordinates) of the M512 or M4K memory block, or the M-RAM.
• Fits in MLABs shows whether a block RAM could have been implemented as an MLAB. If it could not, the reason is listed.

Summarizes information about the gigabit transceiver block (GXB) Definition receiver, including the name, data rate, and receiver channel location of each channel.

Summarizes information about the gigabit transceiver block (GXB) Definition transmitter including the name, data rate, and receiver channel location of each channel. This report appears only if the design targets a supported device (AriaIIseries, Cyclone^®IV, and Stratix^®IV GX) for compilation.

Reports information about the gigabit transceiver block (GXB) Definition receiver channel use, implemented with the alt2gxb Intel^® FPGA IP. The report includes parameter values you specified with the parameter editor or by editing a text file. This report appears only if you specified a device with transceivers and the design includes GXB transmitter PLL & GXB receiver PLL Definition.

Reports information about the gigabit transceiver block (GXB) Definition transmitter channel use, which is implemented with the the alt2gxb Intel^® FPGA IP. The report includes parameter values you specified with the parameter editor or by editing a text file. This report appears only if you specified a device with transceivers and the design includes GXB transmitter PLL & GXB receiver PLL Definition.

Reports information about GXB transmitter PLL & GXB receiver PLL Definition including the name of the transmitter PLL, output clock frequency, in clock frequency; multiply by and divide by factors; PLL type, VCO range and location in the design.

Reports information about central clock dividers, including the digital reference clock output frequency and core clock output frequency; the divide by factor; the status of the digital reference clock post divider and core clock output post divider, the PCIE x8 receiver mode, and the location in the design.

Reports the amount of trace delay compensation recommended for each LVDS node in a design with dynamic phase alignment turned off that targets a device containing transceivers.

The report lists the node name, pin, a recommendation for additional trace delay in ps, and the estimated TCCS reduction in ps.

Reports a list of the 50 highest fan-out signals that are non-global in the design, in descending order. This report provides information regarding the high fan-out signals in the design that may be difficult to route.

Reports information about the pad-to-core delay chain fan-out for the device. This report appears only if the design includes delay chain Definition. The report lists the following information:

• Source Pin / Fanout shows the pad to core delay chain fan-out source pin and fan-out.
• Pad to Core Index shows the pad to core index value.
• Setting shows the pad to core delay chain fan-out setting as an integer.

Summarizes information about enhanced PLL Definition in Cyclone^® and Stratix^® series devices, and enhanced PLL Definition and fast PLL Definition in supported device (Arria^® II Series, Stratix^®IV, and Stratix^®V) families. This report appears only if the design includes PLLs. The report lists the following information:

• PLL type shows the type of PLL.
• SDC pin name lists the SDC compatible name for the given PLL.
• Scan chain shows the value specified for the scan chain option.
• PLL mode shows the mode in which the PLL is operating.
• Feedback Source shows the feedback source for the PLL.
• Compensate Clock shows the mode of the PLL compensation clock.
• Compensated input/output pins lists the compensated input pins when the specified PLL is in source-sync mode and the compensated output pins when the PLL is in zero delay buffer mode.
• Switchover on loss of clock shows whether the PLL uses Switchover on loss of clock.
• Switchover counter shows the value of the PLL switchover counter.
• Primary clock shows which clock acts as the primary clock for the PLL.
• Input frequency clock0 shows the input frequency, in MHz, for input clock 0.
• Input frequency clock1 shows the input frequency, in MHz, for input clock 1.
• Nominal VCO frequency shows the value of the nominal VCO frequency, in MHz, for the PLL.
• VCO frequency control shows the method of frequency control, which is auto, manual phase, or manual frequency.
• VCO phase shift step shows the phase shift increment, in picoseconds, for each dynamic phase-shift step.
• DPA multiply shows the dynamic phase alignment multiplication value of the specified PLL.
• DPA divide shows the dynamic phase alignment division value of the specified PLL.
• DPA divider counter value shows the dynamic phase alignment divider counter value of the specified PLL.
• Freq min lock shows the minimum lock input frequency, in MHz, for the PLL.
• Freq max lock shows the maximum lock input frequency, in MHz, for the PLL.
• Clock Offset shows the clock offset value.
• M VCO Tap shows the VCO tap value for the M counter.
• M Initial shows the number of initial VCO cycles before the M counter starts.
• M value shows the value of the M counter.
• N value shows the value of the N counter.
• M counter delay shows the delay value for the M counter.
• N counter delay shows the delay value for the N counter.
• M2 value shows the spread spectrum modulus for the M counter.
• N2 value shows the spread spectrum modulus for the N counter.
• SS counter shows the value for the spread spectrum counter for the PLL.
• Downspread shows the downspread percentage for the PLL.
• Spread frequency shows the spread frequency, in MHz, for the PLL.
• Charge pump current shows the charge pump current value, in mA, for the PLL.
• Loop filter resistance shows the resistance, in Ω, for the loop filter R resistor.
• Loop filter capacitance shows the capacitance, in pF, for the loop filter C capacitor.
• Freq zero shows the frequency zero for the PLL.
• Bandwidth shows the bandwidth , in MHz or kHz, for the PLL.
• Freq pole shows the frequency pole, in MHz, for the PLL.
• Enable0 counter shows which PLL counter is used by the enable0 input port of the differential I/O clock.
• Enable1 counter shows which PLL counter is used by the enable1 input port of the differential I/O clock.
• Real time configurable shows whether the real time configuration option is turned on for the PLL.
• Bitstream for reprogramming shows the hexadecimal bit stream needed for reprogramming the PLL in real time. The bit stream should be shifted in from left to right: the first bit to shift in is the left-most bit shown in the Bitstream for reprogramming value. The transfer enable bit is included in the bit stream value, is logic level high, and is shifted in first (that is, the left-most bit of the bitstream always has a value of one).
• Scan chain MIF file shows the Memory Initialization File (.mif) Definition generated by the compiler to represent the initial state of the scan chain. The indicated file can be used with the altpll_reconfig Intel^® FPGA IP to dynamically reprogram the PLL. Bit0 in the Memory Initialization File is the first bit to shift in. The transfer enable bit is not included in the bit stream and is generated by the altpll_reconfig Intel^® FPGA IP.
• PLL Location shows the location of the PLL.
• Preserve PLL counter order shows whether thePreserve PLL counter orderlogic option is turned on or off for the specified PLL.
• Inclk0 signal and Inclk1 signal show the primary pins feeding the signal to the specified PLL.
• Inclk0 signal type and Inclk1 signal type show the signal source types.

Reports usage information about enhanced PLL Definition in Cyclone^® and Stratix^® series devices, and enhanced PLL Definition and fast PLL Definition in supported device (Arria^® II Series, Stratix^®IV, and Stratix^®V) families. This report lists the values of the specific output clock(s) for the PLLs in the design. This report appears only if the design includes PLLs. The report lists the following information:

• Name shows the instance name of the PLL.
• Output Clock shows the output clock you specified for the PLL.
• Mult shows the multiplication factor for the PLL output clock.
• Div shows the division factor for the PLL output clock.
• Output Frequency shows the clock frequency value for the PLL output port. This value is equal to the input frequency multiplied by the multiplication factor for the PLL output port, and divided by the division factor for the PLL output port.
• Phase Shift shows the value you specified for the phase shift, measured in degrees and picoseconds, of the PLL output clock.
• Phase Shift Step shows the phase shift increment, in degrees of output frequency and picoseconds, for each dynamic phase-shift step of the specific output clock.
• Delay shows the time delay, in picoseconds, you specified for the PLL output clock.
• Duty Cycle shows the duty cycle of the clock.
• Counter shows the counter value you specified for the PLL output clock.
• Counter Delay shows the counter delay, in picoseconds, you specified for the PLL output clock.
• Counter Value shows the counter value (<counter value> | Bypass) for the PLL. This value is equal to the sum of the high and low cycles specified for the PLL. Bypass is shown if there are no high or low cycles specified for the PLL.
• High/Low shows the number of high and low cycles for the PLL.
• Initial shows the number of initial VCO cycles before the counter starts.
• VCO Tap shows the VCO tap value for the counter.
• SDC Pin Name lists the SDC compatible name for the given PLL.