ID:13700 VHDL Variable Declaration warning at <location>: ignored initial value expression for the variable

CAUSE: In a Variable Declaration at the specified location in a VHDL Design File (.vhd), you specified an initial value expression (or power-up state) for the specified variable. However, you also update the variable's value during simulation by assigning the variable a new value using a Block Statement. Because it cannot generate logic to ensure a non-constant variable's power-up state matches its initial value expression, Quartus Prime Integrated Synthesis ignored the initial value expression you specified for the variable. As a result, the synthesized design's power-up state may differ from its simulated power-up state.

ACTION: If this behavior is correct, no action is required. To avoid receiving this message in the future, remove the initial value expression from the Variable Declaration. If the design requires that a non-constant variable power up to a particular value, rewrite the design so that Quartus Prime Integrated Synthesis infers a register for the variable. You can then specify the power-up state of the register using an explicit reset condition. In some cases, you may receive this message for variables that act as temporary buffers within Process Statements. In VHDL, the state of a variable declared in a Process Statement persists between separate evaluations of the Process Statement. Therefore, if you intended to initialize a variable prior to each execution of the Process Statement, remove the initial value expression from the variable's declaration and replace it with an explicit initialization assignment in the Process Statement itself.