ID:13440 Verilog HDL Module Instantiation error at <location>: ignoring trailing ordered association

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you either accidentally entered duplicate commas at the end of the port connection list, or you used named port connections followed by ordered port connections; port connections must be all by order or all by name; the two types cannot be mixed. Quartus Prime Integrated Synthesis is ignoring the duplicate commas or ordered port connections.

ACTION: No action is required. To avoid receiving this message in the future, remove any duplicate commas, and make sure the Module Instantiation does not include mixed ordered and named port connections.