ID:13466 Verilog HDL Port Declaration warning at <location>: data type declaration for "<name>" declares dimensions but the port declaration declaration does not

CAUSE: In a port declaration at the specified location in a Verilog Design File (.v), you declared the specified object without packed/unpacked dimensions. However, you declared one or more packed/unpacked dimensions in the object's data type declaration. When multiple declarations for an object do not agree on the number of packed/unpacked dimensions, Quartus Prime Integrated Synthesis follows the data type declaration, not the port declaration. That is, if the data type declaration declares packed dimensions, then the object has those packed dimensions; otherwise, the object has no packed dimensions, regardless of the packed dimensions declared in the port declaration. For example, the following code fragment declares a port data with inconsistent declarations:

output status;
reg [7:0] status; // status has a single packed dimension with range [7:0]