ID:14884 Verilog HDL Module Instantiation error at <location>: module instance port connections cannot be mixed -- port connections must be all by order or all by name

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you instantiated a module, but specified some of the port connections in ordered form, and others in named form. Port connections must be all by order or all by name; the two types cannot be mixed.

ACTION: Connect the ports in the Module Instantiation either all by name or all by order.