ID:13482 Verilog HDL Function Declaration warning at <location>: function "<name>" may return a Don't Care value because its output register may not be assigned a value in every possible path through the function

CAUSE: In a Function Declaration at the specified location in a Verilog Design File (.v), you declared the specified function. However, you may not have assigned a value to the function's output register in every possible path through the function. As a result, certain input values may cause the function to return a Don't Care value. For example, in the following code, the function foo assigns a value to its output register only when sel == 1'b1. For all other values of sel, the function returns a Don't Care value.

function foo;
   input sel, a;
begin
   if(sel)
      foo = a;
end
endfunction

            

The following code also shows an example of a function that returns a Don't Care value. In this example, the Case Statement is incomplete because values of the Case Statement expression, which is the 2-bit reg variable sel, are not used in any of the case item expressions in the Case Statement. sel has a total of four possible binary values: 2'b00, 2'b01, 2'b10, and 2'b11 (Quartus Prime Integrated Synthesis considers only binary values when computing the input value set for a Case Expression). However, the case item expressions cover only three of the input values; no case item expression exists for sel == 2'b11. Therefore, the function foo does not assign a value to its output register when sel == 2'b11; instead, the function returns a Don't Care value.

function foo;
   input [1:0] sel;
   input a, b, c;
 
               
begin
   case(sel)
       2'b00:  foo = a;
      2'b01:  foo = b;
      2'b10:  foo = c;
      -- Missing Case Item for sel == 2'b11
   endcase
end
endfunction