ID:13476 Verilog HDL Event Control warning at <location>: posedge or negedge of vector "<name>" depends solely on its least-significant bit

CAUSE: In an Event Control at the specified location in a Verilog Design File (.v), you tested for a positive or negative edge on the specified vector variable or multibit expression. The Verilog language defines an an edge transition on a vector or multibit expression as an edge transition on the least-significant bit in the vector variable or multibit expression. Thus, the edge transition does not depend on all the bits in the variable or expression. This behavior may not match your intentions.

ACTION: To avoid receiving this message in the future, use only single bit variables or expressions in negedge or posedge tests.