ID:13316 Verilog HDL unsupported feature warning at <location>: Disable Statement is not supported, and is ignored in compilation

CAUSE: In a Block Statement at the specified location in a Verilog Design File (.v), you used a Disable Statement. However, although Disable Statements are supported in Verilog HDL, they are not supported in the Quartus Prime software. Quartus Prime Integrated Synthesis is ignoring the Disable Statement.

ACTION: No action is required. To avoid receiving this message in the future, use an If Statement to specify condition expressions that control the termination condition inside the Block Statement.