ID:13513 Verilog HDL Case Statement warning at <location>: case item expression covers a value already covered by a previous case item

CAUSE: In a case item at the specified location in a Verilog Design File (.v), you used an expression that overlaps with a previous case item expression. When evaluating a case statement, Verilog HDL always executes the first case item with an expression whose value matches the value of the case expression. As a result, this overlapping case item may not execute unless it contains another, non-overlapping case item expression.

ACTION: Check your case items for mistakes. If you want to eliminate this warning, remove the duplicate case item expression or modify it to cover a unique value.