ID:21431 Verilog HDL warning at <location>: interface cannot be used as top-level design unit, ignoring '<string>' from design statement

CAUSE: Intel Quartus Prime Synthesis generated the specified warning message for the specified location in a Design File.

ACTION: No action is required. To remove the warning, address the issue identified by the message text. A future version of the Intel Quartus Prime software will provide more extensive Help for this warning message.