ID:13281 Verilog HDL or VHDL warning at <location>: conditional expression evaluates to a constant

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you used a condition expression that evaluates to a static constant. That is, the condition expression does not depend on compile-time or run-time information, but can be evaluated fully when Quartus Prime Integrated Synthesis parses the expression during analysis. As a result, some branches of your HDL source code may be unused and have no impact on the design. For example, in the following Verilog HDL code, the If Statement has a constant literal in its condition; consequently, the Else branch is never executed.

always@(a or b) begin
	if(1'b1) begin
		o = a ^ b;
	end
	else begin // this branch is dead code 		o = a | b;
	end
end