ID:188031 Ignored hold transfers: Source clock = <clk1>, Destination clock = <clk2>, Estimated delay added for hold = <delay> ns (<pctg> of available delay)

CAUSE: The clock domain has too much delay added for hold, so the fitter chooses to ignore the hold requirement on this clock domain. This may be due to bad timing constraints.

ACTION: Verify that timing constraints, particularly multicycles, are set properly or set the OPTIMIZE_HOLD_TIMING setting to ALL_PATHS to optimize these paths for hold as well.