ID:335091 The Timing Analyzer found <number of latches> latches that cannot be analyzed as synchronous elements. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Synthesis report.

CAUSE: The Timing Analyzer found latches across multiple look-up tables (LUTs), or latches that do not include an enable (e.g. SR latches). The Timing Analyzer does not support analyzing this latch implementation as a synchronous element, but treats these latches as a combinational loop.

ACTION: You must implement these latches with registers using asynchronous load and data signals, or remove these latches from your design. For more information, run the check_timing tcl command in the Timing Analyzer.