ID:19807 Design contains combinational loop of <number> nodes. The Timing Analzyer cannot estimate delays for such large loops, and all timing paths through this loop will be disabled.

CAUSE: The Timing Analyzer found an extremely large combinational loop. Estimation of loop delays decreases accuracy and effectiveness of timing analysis, and also impacts performance of timing-driven compilation. This loop is so large that the Timing Analyzer cannot estimate the loop delay without extreme runtime and memory consequences. Large combinational loops are usually the result of a design error. When this condition occurs, the Timing Analyzer must ignore all paths through the loop.

ACTION: Examine your design to determine whether the loop is involved in logic paths that are not meeting timing, and if so, remove the loop from your design.