ID:142011 No LogicLock regions detected in the exported post-fit netlist. No-fit error and circuit performance degradation likely in parent project.

CAUSE: You tried to export post-fit results of a project compiled without any LogicLock regions. This is discouraged for two reasons. First, because it increases the possibility of getting a no-fit error resulting from resource allocation conflicts. Second, because it may seriously degrade circuit performance when the exported netlist is compiled under its parent project following importation.

ACTION: Carefully create a floorplan using one or more LogicLock regions. Then, recompile the project and perform exportation again. If this is a team-based design project, try to create the floorplan with other group members. Such joint planning lowers the risk of resource allocation conflicts and also improves overall design quality.