ID:199039 Formal verification not supported for specified design entry/synthesis tool

CAUSE: You specified a formal verification tool for the current project, and compiled the current design. However, formal verification designs is not supported for the selected synthesis tool. This feature is supported for only Synplify and Synplify Pro synthesis tools. As a result, the Quartus Prime software will not create a Verilog Quartus Mapping File (.vqm) netlist or run the tool automatically to synthesize the design.

ACTION: No action is required. If you want to use a formal verification tool, select a synthesis tool that supports this feature.