ID:276021 Created node "<name>" as a single-port RAM by generating altsyncram megafunction to implement register logic. Power-up values at the outputs of the RAM are different from the original design.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified a set of registers that act as a single-port RAM. When Analysis & Synthesis created the specified node as a RAM using the registers, it converted the registers into an altsyncram megafunction to implement the register logic with memory blocks on the target device. The original design specified that RAM output should power up to the value at address 0. However, in hardware the outputs of the memory block power up to 0.

ACTION: If you intended Analysis & Synthesis to convert the registers into an altsyncram megafunction to implement the register logic with a single-port RAM, and you do not mind if the power-up values at the outputs of the memory block are not identical to the power-up values of the RAM outputs in the original design, no action is required. If you want Analysis & Synthesis to use an altsyncram megafunction, but you want to avoid receiving this message in the future, replace the registers and address logic in the Verilog Design File or VHDL Design File with an explicit instantiation of an altsyncram megafunction. If you want the power-up of the RAM in the original design to be the same as the power-up that is implemented in the target device, prevent Analysis & Synthesis from converting the registers into a single-port RAM either by turning off the Auto RAM Replacement logic option or by setting the ramstyle of the specific RAM to logic. If you want the RAM to be implemented in block RAM with the same power-up values as the original design, provide registers at the outputs of the RAM and set a synthesis preserve attribute to the registers holding the read address.