ID:18703 ATX PLL or fPLL < <name> > is configured for the OTN or SDI protocol and is not placed in the same bank as its reference clock source.

CAUSE: For OTN and SDI protocols, Intel recommends the ATX PLL or fPLL and its reference clock be placed in the same transceiver bank for best jitter performance.

ACTION: Place the ATX PLL or fPLL and reference clock input pins in the same transceiver bank.