ID:18782 ATX PLLs <name> and <name> are <number> ATX PLLs apart. For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed <number> ATX PLL apart (skip <number>).

CAUSE: For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed 4 ATX PLL apart (skip 3 intervening ATX PLLs). Intel recommends that you do not place these two ATX PLLs at their current locations. The distance between the two ATX PLLs is too small to meet the spacing requirements.

ACTION: Modify the location constraints for these two ATX PLLs in the Assignment Editor.