ID:18396 EDA simulation disabled for this design

CAUSE: Your design includes IP cores for which Quartus Prime cannot generate programming files. This may be because you do not have a license for these cores. Of these cores, some do not support the Intel FPGA IP Evaluation Mode feature, so even time-limited programming files cannot be produced for this design. Others, however, do support the Intel FPGA IP Evaluation Mode feature. Because of this, Quartus Prime cannot generate the files needed for EDA simulation of this design. The submessage(s) of this message list the cores that do support Intel FPGA IP Evaluation Mode, causing simulation to be disabled.

ACTION: To re-enable Quartus Prime to create files needed for EDA simulation, disable Intel FPGA IP Evaluation Mode under Compilation Settings or More Compilation Settings.