ID:275015 Design name for "<name>" contains a number -- illegal for Verilog HDL and VHDL -- adding "\\" in front of name

CAUSE: You created a Graphic Design File (.gdf), but the BDF or GDF design name contains a number. The design will not compile once it is converted to a Verilog Design File or VHDL Design File .

ACTION: No action is required. The Quartus Prime software changed the name by adding a "\" in front of the name. To avoid receiving this message in the future, name the BDF or GDF without numbers.