ID:176230 Can't pack node "<name>" and I/O node "<name>" because the packing violates global signal capacity constraints of the region of the device occupied by the I/O node

CAUSE: You turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified LCELL or I/O node. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the logic cell into the I/O node because the I/O node device region cannot accommodate an additional global signal.

ACTION: One of the following actions may resolve the issue. Remove or relax location constraints on nodes requiring the global routing resources in the I/O node device region. Set the Global Signal logic option to OFF on some of the signals that are allocated global routing resources in the I/O node device region. You may do this for that entire global signal, or only between that global signal and destination nodes in the specified region. Turn off auto global signal promotion in the project-wide settings. That is, set options Auto Global Clock , Auto Global Register Control Signals , and Auto Global Memory Control Signals to the value OFF.