ID:176596 Corner PLL "<name>" input clock inclk[<number>] is not fully compensated. because it is fed by a center pin "<name>".
CAUSE: The specified PLL is a corner PLL and its specified input clock is driven by a center input pin. As a result, input clock delay will not be fully compensated by the PLL.
ACTION:
- No action is required if you do not care about compensation of the specified input clocks.
- For compensation of the input clocks of the specified PLL, place the PLL in a center PLL location and connect the input clocks to dedicated center clock input pins.