ID:176598 PLL "<name>" input clock inclk[<number>] is not fully compensated because it is fed by a remote clock pin "<name>"

CAUSE: The specified PLL and its specified input clock are driven by a remote clock input pin. As a result, the input clock delay may not be fully compensated by the PLL.

ACTION: If you do not care about compensation of the input clock(s), use the no compensation mode instead. Otherwise, connect the input clock to a dedicated clock input pin.