ID:308067 (High) <text>. (Value defined:<number>). Found <number> asynchronous clock domain interface structure(s) related to this rule.
CAUSE: In the current design, the Design Assistant found the specified number of structures where single-bit data is transferred between asynchronous clock domains; however, the synchronization of the data bits does not follow one or more of the following guidelines and therefore causes metastability problems in the design:
- Each data bit should be synchronized with two cascading registers in the receiving asynchronous clock domain.
- The cascading registers should be triggered on the same clock edge.
- There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
ACTION: Correctly synchronize all the data bits.
CAUSE: In the current design, the Design Assistant found the specified number of structures where multiple-bit data is transferred between asynchronous clock domains; however, the synchronization of the data bits does not follow one or more of the following guidelines and therefore causes metastability problems in the design:
- The data bits that act as REQ (Request) and/or ACK (Acknowledge) signals should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.
- The cascading registers should be triggered on the same clock edge.
- There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
ACTION: Correctly synchronize the data bits that act as REQ and/or ACK signals.