ID:308048 (Critical) <text>. Found <number> pulse generator(s) related to this rule.
CAUSE: In the current design, the Design Assistant found the specified number of pulse generators, which are structures that generate pulses in one of the following ways:
- By increasing the width of a glitch using a two-input AND, NAND, OR, or NOR gate, where the source for the two gate inputs are the same, but the design inverts the source for one of the gate inputs.
- Using a register where the register output drives the register's own asynchronous reset signal through a delay chain (one or more consecutive nodes that act as a buffer for creating intentional delay).
ACTION: Implement the pulse generator synchronously so the pulse width is always equal to the clock period.