ID:15058 PLL "<name>" is in normal or source synchronous mode with output clock "<name>" set to clk[<number>] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins

CAUSE: The specified PLL is in normal or source synchronous mode and has the specified compensated output clock feeding an output pin. As a result, the output pin will not be fully compensated because only PLLs in zero delay buffer mode can fully compensate output pins.

ACTION: If you do not want to compensate output pins in the specified PLL, no action is required, or you can set the PLL to no compensation mode to avoid this warning. If you want to compensate another register destination, use the COMPENSATE_CLOCK parameter to specify the specified clock output, or set the PLL to zero delay buffer mode to fully compensate the output pin.