ID:15357 WYSIWYG primitive "<name>" has clock enable port <name>[<index>] that is driven by GND

CAUSE: The specified clock enable port of the specified WYSIWYG primitive is driven by GND. When a port is driven by GND, the registers are disabled and the registered signal will remain at its current power_up value.

ACTION: If you are bypassing a register driven by the clock enable port, modify the design so that the register is set to NONE. If you are setting a constant value for the registered signal, modify the design so that the registered signal is set to V_CC or GND and the register is set to NONE.