ID:15735 Ignored Virtual Pin logic option on PLL input clock pin "<name>" -- logic option is illegal for PLL input clock pins

CAUSE: You assigned the PLL input clock pin. However, this logic option assignment is illegal for PLL input clock pins. When this condition occurs, Analysis & Synthesis ignores the Virtual Pin assignment for the pin.

ACTION: No action is required. However, to avoid receiving this message in the future, remove the Virtual Pin assignment from the pin.